Sascha Breun
M. Sc. Sascha Breun, Akad. Rat
Department Elektrotechnik-Elektronik-Informationstechnik (EEI)
Lehrstuhl für Technische Elektronik
Cauerstraße 9
91058 Erlangen
- Telefon: +49 9131 85-27193
- Faxnummer: +49 9131 85-28730
- E-Mail: sascha.breun@fau.de
- Webseite: http://www.lfte.de
Lebenslauf
Sascha Breun received the M.Sc. degree in Electronic Engineering (EEI) from the Friedrich-Alexander University of Erlangen-Nuremberg in 2018. In Juli 2018, he joined the Institute for Electronics Engineering, Friedrich-Alexander University of Erlangen-Nuremberg, Germany, as a Research Assistant. His research interests include RF integrated circuit and system design.
Publikationen
2022
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A 268-325 GHz 5.2 dBm Psat Frequency Doubler using Transformer-Based Mode Separation in SiGe BiCMOS Technology
2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) (, 6. Dezember 2021 - 9. Dezember 2021)
DOI: 10.1109/BCICTS50416.2021.9682474
BibTeX: Download - , , , , :
A 295-337 GHz 2.5 dBm Psat Cascode-Based Frequency Doubler in SiGe BiCMOS Technology
2022 IEEE 22nd Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) (Las Vegas, 16. Januar 2022 - 20. Januar 2022)
DOI: 10.1109/SiRF53094.2022.9720049
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A 220-325 GHz Subharmonic Receiver with 14.8 dB Peak Conversion Gain for FMCW Radar in SiGe BiCMOS Technology
IEEE Radio & Wireless Week (Las Vegas, 16. Januar 2022 - 19. Januar 2022)
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2021
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A 314-344 GHz Frequency Doubler with Driving Stage and 1 dBm Psat in SiGe BiCMOS Technology
IEEE Radio & Wireless Week (Virtual Conference, 18. Januar 2021 - 22. Januar 2021)
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2020
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Extended Equivalent Circuit Model for Enhanced Substrate Modeling of Three-Port Inductors
RWW 2020 (, 26. Januar 2020 - 29. Januar 2020)
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A Low-Power 14% FTR Push-Push D-Band VCO in 130 nm
SiGe BiCMOS Technology with -178 dBc/Hz FOMT
RWW 2020 (, 26. Januar 2020 - 29. Januar 2020)
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2019
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Analytical Equivalent Circuit Extraction Procedure for Broadband Scalable Modeling of Three-Port Center-Tapped Symmetric On-Chip Inductors
In: IEEE Transactions on Circuits and Systems I-Regular Papers 66 (2019), S. 3557-3570
ISSN: 1549-8328
DOI: 10.1109/TCSI.2019.2926737
BibTeX: Download - , , , , , , , , :
A Highly Linear and Efficient 28 GHz Stacked Power Amplifier for 5G using Analog Predistortion in a 130nm BiCMOS Process
IEEE Asia-Pacific Microwave Conference (APMC) (Singapore, 10. Dezember 2019 - 13. Dezember 2019)
In: PROCEEDINGS OF THE 2019 IEEE ASIA-PACIFIC MICROWAVE CONFERENCE (APMC), NEW YORK: 2019
BibTeX: Download - , , , , , , , , , , , , , :
Design of an Integrated Subretinal Implant Using Cellular Neural Networks for Binary Image Generation in a 130 nm BiCMOS Process
IEEE Engineering in Medicine and Biology Conference (EMBC) (Berlin, 23. Juli 2019 - 27. Juli 2019)
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Design Methodology for Automatically Designed, Integrated Marchand Baluns with Low Insertion Loss at Lowest Phase Imbalance
APMC (Asia-Pacific Microwave Conference) (Singapur, 10. Dezember 2019 - 13. Dezember 2019)
DOI: 10.1109/APMC46564.2019.9038425
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A Signal Source Chip at 140 GHz and 160 GHz for Radar Applications in a SiGe Bipolar Technology
MWSCAS (Dallas, 4. August 2019 - 7. August 2019)
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